Tradeoffs between gate oxide leakage and delay for dual T/sub ox/ circuits

Abstract

Gate oxide tunneling current (Ig,,,) will become the dominant component of leakage in CMOS circuits a the physical azide thickness Po=) goes below 15A. Increasing the value of To, reduces the leakage at the expense of an increase in delay, and a pmctical trade08 between delay and leakage can be achieved by assigning one of the two permissible To, values to each transistor. In this paper, we propose an algorithm for dual To, assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tmdeoff cnwe. As compared to the case where all transistors are set to low To=, our approach achieves an average leakage reduction of 8% under lOOnm models. of the barrier height (i.e., the voltage drop across gate oxide) and the barrier thickness, which is simply To,, and a small change in To, can have a tremendous impact 011 Igat.. For example, in MOS devices with Si02 gate oxides, a difference in To, of only 2A can result in an order of magnitude increase in Ipote [Z], so that reducing To; from 1SA to lZA increases Isat. by approximately 100Ox. The other component of leakage, subthreshold leakage ( Iaub) , forms a reducing fraction of the total leakage as To, is reduced, so that Ipote will become the dominant leakage mechanism in the future. The most effective way to control I,,,, would be through the use of high-k dielectrics, but such materials are not expected before the 65nm technology node in 2007, a t the earliest.

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